View FTH datasheet from FTDI, Future Technology Devices International Ltd at Digikey. FTH are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for FTH. FTHQ-TRAY FTDI USB Interface IC Sgl Mbs 2 UART USB 12Mbit datasheet, inventory & pricing.
| Author: | Zulkikree Kagazragore |
| Country: | Italy |
| Language: | English (Spanish) |
| Genre: | Life |
| Published (Last): | 17 September 2015 |
| Pages: | 446 |
| PDF File Size: | 20.43 Mb |
| ePub File Size: | 3.70 Mb |
| ISBN: | 398-5-44786-439-7 |
| Downloads: | 77218 |
| Price: | Free* [*Free Regsitration Required] |
| Uploader: | Dikus |
It has the capability of being configured in a variety of industry standard serial or parallel interfaces. The FTH has the following advanced features: Entire USB protocol handled on the chip. No USB specific firmware programming required.
Independent Baud rate generators. RS Data Rate limited by external level shifter. MCU host bus emulation mode configuration option. Fast Opto-Isolated serial interface option.
FTDI click
Adjustable receive buffer timeout. Option for transmit and receive LED drive signals on each channel. Asynchronous serial UART interface option with full hardware handshaking and modem interface signals.
Low operating and USB suspend datashedt. Supports bus powered, self-powered and highpower bus powered USB configurations. Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or re produced in any material or electronic form without the prior written consent of the copyright holder.
This produc t and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied.
Future Technology Devices International Ltd will n ot accept any claim for damages howsoever arising as dstasheet result of use or failure of this product. Your statu tory right s are not affected. This product or any varian t of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury.
Mini-Module FTH — PlatformIO a1 documentation
This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual propert y rights is implied by the publication of this document. Scotland Registered Company Number: FT D I 77 The following additional installation guides application notes and technical notes are also available: Packaging code for xxxx is: For USB compliance these may require a slight adjustment.
Timing can also be changed by adding appropriate passive components to the USB signals. This pin numbering is illustrated in the schematic symbol shown in Figure 3. The function of many pins is determined by the configuration of the FTH. The following table details the function of each pin dependent on the configuration of the interface.
Each of the functions is described in the following table Note: The convention used throughout this document for active low signals is the signal name followed by. C ore supply voltage input. It is recommended that this supply is filtered using an LC filter. Note that this cannot be connected directly to the USB supply.
Integrated voltage regulator output. FT D I 77 Active low power-enable output. This can be used by datasueet circuitry to power down logic when device is in USB suspend or has not been configured. USB Power Save input. Tri-State during device reset. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.
FT2232H Datasheet
Also see note 1, 2, 3 in section 4. For use with RS level converters. This should be connected to an LED. Channel A Pin No. This bus is normally input unless OE is low.
When high, do not read data from the FIFO. Note that the OE pin must be driven low at least 1 clock period before asserting RD low. D7 when RD goes low. Enables the data byte on the D All signals should be synchronized to this clock. Output enable when low to drive data onto D This should be driven low at least 1 clock period before driving RD low to allow for data buffer turn-around.
Normally, this can be used to wake up the Host PC. This can be used to optimize USB transfer speed for some applications. In this mode, data is written or read on the falling edge of the RD or WR signals. This bus is normally input unless RD is low.
When RD goes high again RXF will always go high and only become low again if there is another byte to read. When high, do not write data into the FIFO. Writes the data byte on the D There are two types of bit-bang modes: When configured in any bit-bang mode, the pins used and the descriptions of the signals are shown in Table 3. The FPGA device would normally be un-configured i. This data would define the hardware function on power up.
The other FTH channel would be available for another function.
When configured in this mode, the pins used and the descriptions of dattasheet signals are shown Table 3. Not available on channel A. A proprietary FTDI protocol designed to allow galvanic isolated devices to communicate synchronously with the FTH using just 4 signal wires over two dual opto-isolatorsand two power lines.
The peripheral circuitry controls the data transfer rate in both directions, whilst maintaining full data integrity. Maximum USB full speed data rates ft2232n be achieved. When configured in this mode, the pins used and the de scriptions of the signals are shown in Table 3.
Fast serial clock input. C lock input to FTH chip to clock data in or out. Fast serial data output. Fast serial C lear To Send signal output. Driven low to indicate that the chip is ready to send data Table 3. Outputs the clock signal being used by the configured interface.
In addition this pin has instructions which will make the controller wait until it is high, or wait until it is low. This can be used to connect to an IRQ pin of a peripheral chip. The FTH will wait for the interrupt, and then read the device, and pass the answer back to the host PC.
Th e part number is as FTHQ to distinguish from the pin package type. All the functions are supported in the pin VQFN package. The pin numbering is illustrated in the schematic symbol shown in Figure 3. The function of many pins is determined by the configuration of the FTHQ.
Each of the functions is described in Table 3. The FPGA device would normally be un -configured i. A proprietary FTDI protocol designed to allow galvanic isolated devices to communicate synchronously with the FTH Q using just 4 signal wires over two dual opto -isolatorsand two power lines. The FTH has two independent configurable interfaces. It also includes 4kbytes Tx and Rx data buffers per interface.
This is really a feature of the driver and is used to as a timeout ft22232h flush short packets of data back to the PC.
The default is datzsheet, but it can be altered between 0ms and ms. At 0ms latency you get a packet transfer on every high speed microframe. It also handles power management and the USB protocol specification.
It also provides the clocks for the rest of the chip. This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. In this case, the device will not have a serial number as part of the USB descriptor. The FT can be configured as a mixture of these interfaces.
This can be repeated for channel B to provide a dual RS, but ft222h been omitted for clarity. It has separate enables on both the transmitter and receiver. RS is a multi-drop network — i. The RS cable requires to be terminated at each end of the cable.